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SNAD01C
8-CHANNEL 8-BIT ADC
========
1. 2. 3. 4. 5. 6.
CONTENTS
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GENERAL DESCRIPTION ..........................................................................................................................3 FEATURES ...................................................................................................................................................3 APPLICATIONS............................................................................................................................................3 BLOCK DIAGRAM .......................................................................................................................................4 PIN ASSIGNMENTS.....................................................................................................................................4 Functional Descriptions .............................................................................................................................5 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Interface Format...................................................................................................................................5 Channel Setting ...................................................................................................................................7 Control Register Setting ......................................................................................................................7 ADC Read Timing................................................................................................................................8 Timing of Digital Input Reading...........................................................................................................9 Power Down & Channel Wake-Up ...................................................................................................10 Bandgap reference............................................................................................................................11 Input Channel PAD (Channel 0~6)...................................................................................................12 Battery Monitoring (Channel 7 only) .................................................................................................13
7. 8. 9.
ELECTRICAL CHARACTERISTICS ........................................................................................................14 APPLICATION CIRCUITS .........................................................................................................................15 EXAMPLE PROGRAMS............................................................................................................................16 9.1. 9.2. 9.3. 9.4. 9.5. Program 1: Set Configuration of SNAD01C....................................................................................23 Program 2: Read ADC result from Channel 1 ................................................................................23 Program 3: Read Digital Input data from Ch4, Ch3, CH2 ..............................................................23 Program 4: Power-down SNAD01C and Host, and Wake-up ........................................................23 Program 5: Battery Low Detection....................................................................................................24
10. PAD DIAGRAM ..........................................................................................................................................26
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8-CHANNEL 8-BIT ADC
AMENDMENT HISTORY Version Ver 1.1 Ver 1.4 Date February 12, 2003 March 18, 2003 Description First issue. Page3: wording modification in FEATURES list Page8: modify Table-3 control register setting Page10: modify Figure-10 Page11: "enters into power down mode at the 8th clock cycle" Page11: more descript about power-down mode setting Page24: add command "@Set_Control_Reg #0, #1, #0, #0" in demo program to make sure turn off RF & MB before power-down 1. Add version code "C" of chip no. 2. Add one item in electrical characteristics 3. Page23: MB=1 4. This spec is modified form SNAD01_V1.4
Ver 1.5
July 31, 2003
Note: This document is used to identify the different version "B" & "C" of SNAD01, the most important is standby current and power down setting between version "B" & "C". For the detail please refer to related section.
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1. GENERAL DESCRIPTION
SNAD01C is a low cost serial 8-bits ADC with 8 individual input channels. Each channel can be independently programmed to a digital or analog input mode. In the analog input mode, this single-ended channel accepts an analog input signal from 0 to VREF and converts the signal into 12-bit digital codes (with 8-bit accuracy guaranteed). In the digital input mode, the channel can be treated as digital input port and the logic level appears at the channel can be acquired. SNAD01C has a synchronous 3-wires serial interface. Through this interface, the host CPU can easily control SNAD01C. During A-to-D conversion, the typical current consumption is 500uA at 25kHz throughput-rate and +3V power supply. SNAD01C includes a power-down mode, which reduces maximum current consumption less than 1uA. The reference voltage can be varied between 1V and +VCC, providing a corresponding input voltage range of 0V to VREF. SNAD01C also has an on-chip 1.17V bandgap reference that can be utilized for constant voltage input (especially for battery monitoring applications). The bandgap reference circuitry consumes 300A@3v and can be enabled and disabled.
2. FEATURES
Single Supply: 2.7V ~ 5.25V Eight Analog/Digital Input Channels. Internal 1.17v Bandgap Reference for Battery Monitoring. (Channel 7) Low Power Consumption: typical operating current: 500uA @ 3V, Standby current <1uA. Up to 25kHz Conversion Rate. 12-bits ADC with 8-bit effective number of bits 3-Wire Serial Interface.
3. APPLICATIONS
Battery-Powered Systems Instrumentation Portable Data Logging Test Equipment Data Acquisition Process-Control Monitoring Digital Input Bus Extender
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4. BLOCK DIAGRAM
AVDD VDD D
1.2V Bandgap Reference
VRH
CH0/DI0 CH1/DI1 CH2/DI2 CH3/DI3 CH4/DI4 CH5/DI5 CH6/DI6 CH7(BAT)/DI7
8-Channels Analog/Digital Input MUX
12 Bit SAR ADC
Serial Interface and Control Logic
START CLK DIO
AVSS
VSSD
Figure-1 Block diagram of ADC
5. PIN ASSIGNMENTS
Pin Name CH[7] ~ CH[0] REF VDD VSS AVDD AVSS START CLK DIO I/O I I I I I I I I IO Description Analog input / digital input Reference voltage of analog signal Positive power Negative power Positive power of analog circuit Negative power of analog circuit Command initialization signal (from host controller) Clock of data communication and AD conversion (from host controller) Data input and output of data communication Table-1
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6. Functional Descriptions
VDD
Host CPU
Output Port1 Output Port2 I/O port START CLK DIO START CLK DIO
SNAD01
VDD AVDD REF 0.1uF VSS AVSS
CH[0] CH[1] Analog/Digital Signal
CH[7]
Figure-2 Interface with Host CPU
6.1. Interface Format
START CLK
Channel Setting
HiZ
DIO
CM2
CM1
CM0
CH[7] CH[6] CH[5]
CH[4] CH[3]
CH[2]
CH[1]
CH[0]
X
X
X
X
X
Port Input
Control Register Setting
HiZ
DIO
CM2
CM1
CM0
PH
PL
RF
MB
X
X
X
X
X
X
X
X
X
Port Input
Digital Input Reading
HiZ
DIO
CM2
CM1
CM0
DI[7]
DI[6]
DI[5]
DI[4]
DI[3]
DI[2]
DI[1]
DI[0]
DI[7]
DI[6]
DI[5]
DI[4]
DI[3]
Port Input
Power Down
HiZ
Port Output
DIO
CM2
CM1
CM0
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
PDS
Port Input
Port Output
Figure-3 Timing Diagram of Whole Commands
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(1) (2) (3) (4) (5)
DIO is HiZ while START is HIGH. The interface logic begins to interpret a command at the falling edge of the START signal. The command ID (sent by Host) is received in the first three clock cycles from DIO. The operations include Channel setting, ADC Reading, Digital Input Reading and Power Down. DIO becomes to HiZ while START returns to HIGH.
Command ID 000 001 010 Power Down (0)
Operation
Channel Attribute Setting (1:Analog, 0:Digital) Channel Wakeup Function Setting (1:Enable, 0:Disable)
011 100 101 110 111
Control Register Setting ADC Conversion Digital Input Reading Reserved Power Down (1) Table-2 Command Description Table
a. b. c. d. e. f. g.
000/111: ADC enters into power down after receiving this command. 001: Set the attribute of each channel to be an analog or a digital input with the sequence of channel 7 to 0. (1:Analog; 0:Digital) 010: Set the wakeup function of each channel to be enabled or disabled with the sequence of channel 7 to 0. (1:Enable; 0:Disable) 011: Setting the values of control registers. 100: ADC starts to convert the analog signal of the selected channel after receiving this command. 101: ADC starts to read the digital input of every channel with the sequence of channel 7 to 0. 110: ADC enters into testing mode.
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6.2. Channel Setting
START CLK
Channel Setting
HiZ
DIO
CM2
CM1
CM0
CH[7] CH[6] CH[5]
CH[4]
CH[3] CH[2] CH[1]
CH[0]
X
X
X
X
X
Port Input
Figure-4 The timing diagram of channel attribute/wakeup setting (1) (2) Command 001: channel attribute setting. Command 010: wakeup function setting.
In attribute setting, "1" means analog and "0" means digital. In wakeup setting, "1" means enable and "0" means disable. After all of the channels are set, the DIO port remains input mode and all the following data are ignored.
6.3. Control Register Setting
START CLK
Control Register Setting
HiZ
DIO
CM2
CM 1
CM0
PH
PL
RF
MB
X
X
X
X
X
X
X
X
X
Port Input
Figure-5 The timing diagram of control registers setting (1) (2) (3) Command ID: (011) 4-bit data behind command ID are loaded into control registers with the sequence of PH, PL, RF and MB. The function of each control registers are as Table-3.
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Name PH PL
Function Set the pull-up resistor of the channel in digital input mode. 1:ON, 0:OFF. Set the pull-down resistor of the channel in digital input mode. "1": ON, "0": OFF.
RF, MB Set the reference source (from internal bandgap or "REF" pin) RF=0, MB=1: reference voltage from "REF" pin RF=1, MB=0: reference voltage from internal bandgap Table-3
Note: 1. The condition of both PH=1 and PL=1 is prohibited. 2. Pull-up and pull-down resistors are not activated while the corresponding channel is set as analog input mode. 3. Before into power down mode, the "RF" and "MB" register must set up "0", otherwise the standby current will more than 1uA.
6.4. ADC Read Timing
START CLK tACQ DIO HiZ 1 0 0 ID2 ID1 ID0 xx xx D7 D6 D5 D4 D3 D2 D1 D0 PDS
Port Input
Port Output
Figure-6 The timing diagram of ADC reading
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(1) (2) (3)
(4)
(5)
Command ID: (100) 3-bit channel number data behind command ID. The analog signal of the selected channel is sampled to ADC. ADC refers the reference voltage and converts the sampled analog signal to digital domain by successiveapproximation method. The 8-bit output data (result of conversion) of ADC is sent to DIO port from MSB and is triggered by CLK. The maximum clock frequency is 500kHz @ 2.7v. (Maximum conversion rate=25KHz) After the 8-bits ADC data has been sent out, if the START is kept in LOW and CLK is kept in High/Low transition, then the data with uncertain value are kept appearing on DIO. These data can just be ignored. Channel ID[2:0] 000 001 010 011 100 101 110 111 Selected Channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Table-4 Channel Selection Table
6.5. Timing of Digital Input Reading
START CLK
Digital Input Reading
HiZ
DIO
CM 2
CM 1
CM0
DI[7] DI[6] DI[5] DI[4]
DI[3] DI[2]
DI[1] DI[0] DI[7]
DI[6] DI[5] DI[4] DI[3]
Port Input
Port Output
Figure-7 The timing diagram of the digital input reading
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(1) (2) (3)
(4)
Command ID: (101). The digital data of each channel is sent to the DIO port with the sequence of channel 7 to 0. After all of the channels are read, if the START is kept in LOW and CLK is kept in HIGH/LOW transition, the digital data of each channel is sent to the DIO port again with the sequence of channel 7 to 0 cyclically. Pulling START to HIGH to terminates this digital input reading.
Note: Once a channel is programmed as analog type, the corresponding data is "0" in digital input reading command.
6.6. Power Down & Channel Wake-Up
START CLK DIO DIO 0 1 0 1 0 1 SNAD01 enters into power-down mode
Figure-8 The timing diagram of power down command
START CLK CH n CH n DIO Wake-Up Host CPU DIO HiZ HiZ Wake-Up Procedure Ending
Figure-9 The timing diagram of power down command
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(1)
(2)
(3)
(4)
The power down command (000/111) is sent to SNAD01C in the first three cycles, and then SNAD01C enters into power down mode at the 8th clock cycle, consuming almost no current (less than 1uA). After SNAD01C enters power down (mode 0: command 000), SNAD01C sends "0" out to DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once the transition occurs, SNAD01C toggles DIO to "1" to inform host controller. After receiving "1" from DIO, host controller should turn START back to "1" to inform SNAD01C that the power-down stage is over. Otherwise, SNAD01C keeps sending out "1" to DIO and does not recognize any other transitions on any channels. After SNAD01C enters power down (mode 1: command 111), SNAD01C sends "1" out to DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once the transition occurs, SNAD01C toggles DIO to "0" to inform host controller. After receiving "0" from DIO, host controller should turn START back to "1" to inform SNAD01C that the power-down stage is over. Otherwise, SNAD01C keeps sending out "1" to DIO and does not recognize any other transitions any the channels. The CLK may stop but START ought to remain at LOW level in the whole power down mode.
(5) The SNAD01C provides two power-down mode "POWER_DOWN 0" and "POWER_DOWN 1", user has to select a property power-down mode that it depend on what kind I/O type for host MCU (pull-up or pull-low) before ADC enter power-down mode. Otherwise, it will generate a DC-path and the standby current also will go up. (6) Before into power down mode, the "RF" and "MB" register must set up "0", otherwise the standby current will more than 1uA.
Note: Wakeup function is only dedicated to the channel which is digital input type AND wakeup-enabled.
6.7. Bandgap reference
VDD
to reference high of the ADC
ON CHIP
OFF CHIP
REF 1.2v bandgap reference VSS
RF
MB
PAD
Figure-10 Circuit diagram of ADC bandgap reference selection
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If the internal bandgap reference is turned ON (RF=1), the reference voltage "VREF" of ADC is from the internal bandgap reference circuit. This internal voltage reference circuit consumes around 300 A, and the output voltage of bandgap reference is around 1.17V typically. If RF is turned off (RF=0), the MB is turned on (MB=1), the reference voltage is from "REF" pin. Otherwise, the reference voltage source is comes from internal bandgap if RF=1 & MB=0.
6.8. Input Channel PAD (Channel 0~6)
VDD ENCH[x]: 1: Analog In / 0: Digital In
PH&ENCH[x]
Pull-high resistor ENCH[x]
CH[x] Pull-low resistor
to ADC
DI[x]
PL&ENCH[x]
VSS
ENCH[x]
Figure-11 Circuit diagram of the Input Channel PAD (1) If any channel is programmed to be analog input mode, then the corresponding internal signal, ENCH[x]=1. As in Figure-11, pull-high and pull-low are disabled. And the path to digital input is blocked. All digital reading operation of this channel will get the result "0". If any channel is programmed to digital input mode, then the corresponding internal signal, ENCH[x]=0. As in Figure-11, the path to ADC is removed. While in digital input mode, this input port can be configured to be floating, weak pull-up, or pull-down by setting the control register PH and PL, where PH&PL=1 is forbidden. The pull-up or pull-low resister are both around 500K@3v. The default status (digital/analog, pull up/down) of all the channels are un-know after power on, so initialize each channel to define a correct state should be done after power on. Mode of each channel (ENCH[x]) can be set by command 001.
(2) (3)
(4) (5)
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6.9. Battery Monitoring (Channel 7 only)
VDD ENCH[7] PH&ENCH[x] DI[7]
CH[7]
30k
20k 10k
ENCH[7]
to ADC
PL&ENCH[x]
Battery VSS
VSS
VSS
Figure-12 The circuit of the Input pad of Channel 7
(1)
While read ADC command is sent and channel 7 is selected, ADC can be used to monitor the battery voltage.
(2) The circuit of battery voltage monitoring is shown in Figure-12 (Channel7 only)
(3) (4) The battery voltage is six times ADC measuring voltage. Thus, the measured result equals to 1/6*battery voltage. While channel 7 is set to the analog input mode, an input resistor (60k) exists from CH[7] to VSS. To save unnecessary power consumption, CH[7] should be switch to digital input type when CH[7] is not measured.
Note: CH[7] is different from the other 7 channels. The input voltage is reduced to 1/6 before it is sent into ADC.
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7. ELECTRICAL CHARACTERISTICS
Typical values apply for VDD=VREF=3.0 V, TAMB=25 C unless otherwise noted.
Symbol Parameter min typ max Unit Conditions
Analog-to-Digital Converter VDD IDD Operating voltage Operating current 2.7 3.0 400 A 5.25 V Excluding bandgap reference and Control Register's RF is set up 0 . VDD=3.0V IPDN FSMP Power Down Current Conversion Rate (Throughput Rate) DNL INL NMC SINAD Differential Nonlinearity Integral Nonlinearity No Missing Code Signal to Noise and Distortion ENOB Effective Number of Bits 8 8 50 0.1 30 40 0.5 -0.5 A kHz LSB LSB Bits dB Bits VDD=2.7~5.25V VDD=3.0V VDD=3.0V VDD=5.0V
Bandgap reference VBG Bandgap reference output 1.14 voltage IBG Operating current of BGR 400 1.17 1.20 V A
Digital Interface Weak pull up/down resistance Output drive/sink current of DIO 3 500k VDD=3V
mA
VOP=VDD-0.5v / VSS+0.5v
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8. APPLICATION CIRCUITS
Example Circuit: SNAD01C works with Sonix 4-bit Series Controller
CH[0], CH[1], CH[2]: Analog Input CH[6]: Digital Input CH[7]: Battery Voltage Detect REF=VDD+
VDD VDD
4-bit Voice chip
P22 P21 P20 VSS START CLK DIO
SNAD02
VDD AVDD REF 0.1uF VSS AVSS
SN100/300/500 SN66/67/68/6A
CH[0] CH[1] CH[2]
Analog Signal Analog Signal Analog Signal
CH[6] CH[7] VDD
Figure-13 SNAD01C works with Sonix 4-bit Series Controller
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9. EXAMPLE PROGRAMS
Host Controller: SNC500. Application circuit is identical to Figure11. P22: START. P21: CLK. P20: DIO. Macro Programs: (def.h)
p2State port_l port_h ad_out_l ad_out_h tmp tmp1 ad_hh equ equ equ equ equ equ equ equ m0 m1 m2 m3 m4 m5 m6 m7 ;;SET START=0
;;******************************** @ON_START macro mov a #1011b and a p2state mov p2state a mov p2 a endm ;;******************************** @OFF_START macro mov a #0100b or a p2state mov p2state a mov p2 a endm ;;******************************** @CLOCK macro mov a #0010b or a p2state mov p2 a mov a #1101b and a p2state mov p2state a mov p2 a endm ;;******************************** @Send_0 macro mov a #1110b and a p2state mov p2state a mov p2 a endm ;;******************************** @Send_1 macro mov a #0001b or a p2state mov p2state a mov p2 a endm ;;******************************** @Send macro data; mov tmp data mov a #1110b and a p2state or a tmp mov p2state a mov p2 a endm ;;********************************
;;SET START=1
;;SET CLK L
H AND H
L
;;HOST SEND 0
DIO
;;HOST SEND 1
DIO
;HOST SEND 1-BIT CONSTANT (#1 OR #0)
DIO
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@Read_DIO macro mov a p2 mov tmp #0001b and a tmp endm ;;******************************** @P20_Out_Mode macro mov a #0000b mov p2s a endm ;;******************************** @P20_In_Mode macro mov a #0001b mov p2s a mov a #1110b and a p2state mov p2state a mov p2 a endm
;;READ DIO
A.0 (1-BIT)
;;SWITCH ALL 4-BIT OF P2 TO OUTPUT MODE
;;SWITCH P2.0 (DIO) TO INPUT MODE
;;************************************************************************** ;; Set Analog/Digital Mode to each channel (1:Analog, 0:Digital) * ;; y7 Ch7. y6 Ch6. y5 Ch5, ... * ;;************************************************************************** @Set_Attrib macro y7,y6,y5,y4,y3,y2,y1,y0 @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_0 @Clock @Send_0 @Clock @Send_1 @Clock @Send y7 @Clock @Send y6 @Clock @Send y5 @Clock @Send y4 @Clock @Send y3 @Clock @Send y2 @Clock @Send y1 @Clock @Send y0 @Clock ;; SEND COMMAND (001)
;; SEND y7 TO y0
@OFF_START ;; SET START=1 @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE endm
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;;************************************************************************* ;; Set Wakeup function Enable/Disable (1:Enable, 0:Disable) * ;; y7 Ch7. y6 Ch6. y5 Ch5, ... * ;;************************************************************************* @Set_Wakeup macro y7,y6,y5,y4,y3,y2,y1,y0 @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_0 ;; SEND COMMAND (010) @Clock @Send_1 @Clock @Send_0 @Clock @Send y7 ;; SEND y7 TO y0 @Clock @Send y6 @Clock @Send y5 @Clock @Send y4 @Clock @Send y3 @Clock @Send y2 @Clock @Send y1 @Clock @Send y0 @Clock @OFF_START ;; SET START=1 @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE endm ;;********************************************************************** ;; Setup Control Register * ;; ph: PULL-HIGH register. pl:PULL-LOW register. * ;; rf: BANDGAP reference enable * ;; mb: Set 0 always * ;;********************************************************************** @Set_Control_Reg macro ph,pl,rf,mb @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_0 @Clock @Send_1 @Clock @Send_1 @Clock @Send ph @Clock @Send pl @Clock @Send rf @Clock @Send mb @Clock ;; SEND COMMAND (011)
;; SEND ph, pl, rf, mb
@OFF_START ;; SET START=1 @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE endm
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;;******************************************************************* ;; Let SNAD01C Enter Power-Down mode 0 * ;;******************************************************************* @Power_Down_0 macro @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_0 ;; SEND COMMAND (000) @Clock @Send_0 @Clock @Send_0 @Clock @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE @Clock @Clock @Clock @Clock @Clock @Clock @Clock @Clock ;; SNAD01C ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE. Endm ;;***************************************************************** ;; Let SNAD01C Enter Power-Down mode 1 * ;;***************************************************************** @Power_Down_1 macro @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_1 ;; SEND COMMAND (111) @Clock @Send_1 @Clock @Send_1 @Clock @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE @Clock @Clock @Clock @Clock @Clock @Clock @Clock @Clock ;; SNAD01C ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE. endm ;;************************************************************************** ;; Read ADC from Channel n (n=n2,n1,n0) ;; e.g.: Ch 5 (n2, n1, n0= #1, #0, #1 ;; 8-bit Data (ad_out_h, ad_out_l) ;; ad_out_h is bit7~bit4 , ad_out_l is bit3~bit0 ;;************************************************************************** @Read_ADC macro n0, n1, n2 @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_1 @Clock @Send_0 @Clock @Send_0 @Clock @Send n2 @Clock @Send n1 @Clock ;; SEND COMMAND (100)
;; SEND CHANNEL NUMBER
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@Send n0 @Clock @p20_in_mode ;; SWITCH P2.0 TO INPUT MODE @Clock ;; WAIT FOR 2 MORE CLOCKS @Clock mov ad_out_l #0 mov ad_out_h #0 ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.3 mov tmp1 #1000b @Read_DIO caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.2 mov tmp1 #0100b @Read_DIO caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.1 mov tmp1 #0010b @Read_DIO caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_h.0 mov tmp1 #0001b @Read_DIO caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.3 mov tmp1 #1000b @Read_DIO caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.2 mov tmp1 #0100b @Read_DIO caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a
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@@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.1 mov tmp1 #0010b @Read_DIO caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in ad_out_l.0 mov tmp1 #0001b @Read_DIO caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @Clock @OFF_START ;; SET START=1 endm ;;***************************************************************** ;; Read Digital Input: * ;; 8-bit Data (port_h, port_l) * ;;***************************************************************** @Read_Port macro @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE @ON_START ;; SET START=0 @Send_1 @Clock @Send_0 @Clock @Send_1 @Clock ;; SET COMMAND (101)
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE mov port_l #0 mov port_h #0 ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_h.3 mov tmp1 #1000b @Read_DIO caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_h.2 mov tmp1 #0100b @Read_DIO caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_h.1 mov tmp1 #0010b @Read_DIO
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SNAD01C
8-CHANNEL 8-BIT ADC
caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_h.0 mov tmp1 #0001b @Read_DIO caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_l.3 mov tmp1 #1000b @Read_DIO caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_l.2 mov tmp1 #0100b @Read_DIO caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_l.1 mov tmp1 #0010b @Read_DIO caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @Clock ;; READ DIO and SAVE 1-bit DATA in port_l.0 mov tmp1 #0001b @Read_DIO caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @Clock @OFF_START ;; SET START=1 endm ;;***************************************
Version: 1.5
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July 31, 2003
SNAD01C
8-CHANNEL 8-BIT ADC
9.1. Program 1: Set Configuration of SNAD01C
;; Setup Configuration of SNAD01C ;; ;; With Pull-Low, use "RF" pin connected external voltage. (PH=0, PL=1, RF=0,MB=1) ;; ;; CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ;; Analog/Digital: B A ADD D A A :B, battery detect ;; Wakeup: X X X NO YES YES X X ;; SNC520 program include def.h START: mov mov mov mov mov a p2s a p2 p2State #1111b a #0000b a #0 #0, #1, #0, #1 #0, #1, #1, #0, #0, #0, #1, #1 #0, #0, #0, #0, #1, #1, #0, #0 ;; Set Control Registers ;; Set Chan Analog/Digital ;; Setup Wakeup function
@Set_Control_Reg @Set_Attrib @Set_Wakeup
9.2. Program 2: Read ADC result from Channel 1
;; Inherit from program 1 ;; 8-bit ADC result of channel 1 in ( ad_out_h, ad_out_l) ;; ad_out_h is bit7~bit4, ad_out_l is bit3~bit0 @Read_ADC ... ... #0, #0, #1 ;;get ADC result from Ch1 in ( ad_out_h, ad_out_l)
9.3. Program 3: Read Digital Input data from Ch4, Ch3, CH2
;; Inherit from program 1 ;; After Reading, ;; Port_h.0 = Input of Ch4 ;; Port_l.3 = Input of Ch3 ;; Port_l.2 = Input of Ch2 @Read_Port ... ... ;; 8-bit Data (port_h, port_l)
9.4. Program 4: Power-down SNAD01C and Host, and Wake-up
;; Inherit from program 1 ;; Enter Power-down Mode (0) @Set_Control_Reg #0, #1, #0, #0 @Power_Down_0 end ... ...
;; Set Control Registers RF and MB is 0 ;;SNAD01C enters power-down Mode (0) ;; HOST (SNC520) enter power-down
Version: 1.5
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July 31, 2003
SNAD01C
8-CHANNEL 8-BIT ADC
TRIGGER: @OFF_START ... @Read_Port
;; SET START=1 ;; READ Trigger condition or Debounce Procedure starting from here
... ...
9.5. Program 5: Battery Low Detection
VDD VDD SNC520 VDD P22 P21 P20 VSS START CLK DIO SNAD01C VDD AVDD REF 0.1uF VSS AVSS CH[7] VDD VDD
Battery: 1.5Vx3
An application uses three 1.5V batteries for power supply. During operation, the power of batteries keeps consumed and the voltage of battery keeps going down. Now, voltage lower than 3.6V is treated as "Battery Low". The ADC and band-gap reference circuit in SNAD01C can be utilized to detect "Battery Low". The voltage through channel 7 to ADC is reduced to 1/6*VDD (Figure10). Thus, when VDD=3.6V, the voltage into ADC is around 0.6V. And bandgap is chosen for reference voltage (approximately 1.17V within the whole operation voltage range). The value acquired from ADC is about (0.6/1.17)*256=131. For simplification consideration, we choose "ADC's readout < 128" as "Battery Low" condition.
Version: 1.5
24
July 31, 2003
SNAD01C
8-CHANNEL 8-BIT ADC
;; Inherit from program 1 ;; Enter Power-down Mode (0) CheckBattery: @Set_Control_Reg @Set_Attrib #0, #1, #1, #0 ;; Set rf=1, turn-on bandgap #1, #1, #1, #0, #0, #0, #1, #1;; Switch Ch7 to Analog
mov m15 #0 CheckAgain: @Read_ADC #1, #1, #1 mov a #1000b and a ad_out_h caje #1000b Battery_Low_No mov a m15 inca mov m15 a caje #3 Battery_Low_Yes jmp CheckAgain Battery_Low_Yes: mov m14 #1 Battery_Low_No: @Set_Control_Reg @Set_Attrib #0, #1, #0, #0
;; Read Ch7 ;; if (Value>=128) then Not Battery Low
;; if (Value<128) for 3 times, then ;; battery low.
;; Set rf=0, turn-off bandgap ;; To save operating current
#0, #1, #1, #0, #0, #0, #1, #1;; Switch Ch7 to Digital
Version: 1.5
25
July 31, 2003
SNAD01C
8-CHANNEL 8-BIT ADC
10. PAD DIAGRAM
NO 1 2 3 4 5 6 7 8 PAD NAME CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 X(um) -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 Y(um) 352.50 242.50 132.50 22.50 -87.50 -197.50 -307.50 -417.50 NO 9 10 11 12 13 14 15 16 PAD NAME VSS VDD DIO CLK START AVDD VSS REF X(um) 623.50 623.50 623.50 623.50 623.50 623.50 623.50 623.50 Y(um) -417.50 -307.50 -197.50 -87.50 22.50 132.50 242.50 352.50
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
1 2 3 4 5 6 7 8
(0,0)
16 15 14 13 12 11 10 9
REF AVSS AVDD START CLK DIO VDD VSS
CHIP SIZE=1350 x 950um
SNAD01C
Note: The substrate MUST be connected to Vss in PCB layout
Version: 1.5
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July 31, 2003
SNAD01C
8-CHANNEL 8-BIT ADC
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Version: 1.5
27
July 31, 2003

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